Design and Implementation of FPGA-Based Systolic Accelerator for Sobel Edge Detection

Abstract

Edge detection is a fundamental operation in digital image processing and embedded vision systems, widely used in surveillance, robotics, autonomous navigation, industrial automation, and object recognition applications.Conventional processor-based image edge detection techniques often suffer from computational limitations when real-time image processing is required.This paper presents the design and implementation of a real-time FPGA-based hardware accelerator for Sobel edge detection using a systolic processing architecture.The proposed system integrates memory interfaces, control peripherals, processing logic, and a custom convolution accelerator into a complete embedded image processing architecture.The accelerator performs streaming image processing through line buffering, parallel gradient computation, magnitude approximation, and pipelined edge generation.Functional validation was performed using benchmark grayscale images under clean, Gaussian noisy, and salt-and-pepper noisy operating conditions.RTL simulation confirms successful edge extraction and robustness under noisy image inputs.Hardware implementation analysis demonstrates efficient resource utilization, stable timing closure, and low power consumption suitable for embedded applications.The proposed design achieves real-time processing capability, demonstrating the effectiveness of hardware acceleration for image edge detection.

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